1. Field of the Invention
The present invention relates to a solid-state imaging apparatus applied to a video camera, a monitor camera, and the like. More particularly, the present invention relates to a solid-state imaging device utilizing a charge transfer function.
2. Description of the Related Art
Solid-state imaging apparatuses are applied to camera systems such as video cameras, monitor cameras, cameras at doors for monitoring visitors, car cameras, cameras for TV phones, cameras for multimedia use, and the like. In recent years, reduction of the size, weight, applied voltage, and cost of such solid-state imaging apparatuses have been requested. In order to realize these requests, the solid-state imaging apparatus generally uses a charge coupled device (CCD). The CCD converts transferred charges into voltages in a potential-floating diffusion layer called a floating diode, and outputs the voltages to an output circuit while sweeping the waste charges used in the charge-voltage conversion processing out to a reset drain. This sweeping of waste charges is realized by applying a reset gate clock to a reset transistor.
FIGS. 7A and 7B illustrate a conventional solid-state imaging apparatus 200: FIG. 7A is a plan view illustrating a CCD imaging section of the solid-state imaging apparatus 200; and FIG. 7B is a view illustrating a circuit construction of a charge-voltage conversion portion and the vicinity thereof of the CCD imaging section.
Referring to FIGS. 7A and 7B, the conventional solid-state imaging apparatus 200 includes a CCD chip 200a which has a function of resolving light from an object to be imaged for each pixel to perform photoelectric conversion and transferring light charges generated by the photoelectric conversion. The CCD chip 200a includes a plurality of photodiodes 1 arranged in a matrix on an n-type substrate 10, vertical CCDs 2, and a horizontal CCD 3. The photodiodes 1 convert incident light to electric charges by photoelectric conversion and accumulate the charges generated by the photoelectric conversion. The vertical CCDs 2 are disposed to correspond to respective columns of photodiodes 1, and transfer the accumulated charges in the vertical direction. The horizontal CCD 3 transfers the charges transferred from the vertical CCDs 2 in the horizontal direction. A charge-voltage conversion section 5 is disposed downstream of the horizontal CCD 3 for converting the charges transferred from the horizontal CCD 3 to voltages. An output circuit 6 is disposed downstream of the charge-voltage conversion section 5. The output circuit 6 has a source follower structure normally composed of a plurality of stages and serves to decrease an output impedance.
A transfer gate 4 is also provided between each photodiode 1 and the vertical CCD 2 for transferring the charges accumulated in the photodiode 1 to the vertical CCD 2.
The charge-voltage conversion section 5, which is formed on the substrate, includes: a floating diode 51 having a charge accumulation region N1 which accumulates charges transferred from the horizontal CCD 3 and is in a potential-floating state; and a reset transistor 52 for draining the charges accumulated in the charge accumulation region N1. The potential value at the charge accumulation region N1 changes depending on the a mount of accumulated charges. An amplifier 6a which constitutes the output circuit 6 amplifies the potential value and outputs an imaging signal to a signal output terminal 50a of the CCD imaging section.
The source of the reset transistor 52 is connected to the charge accumulation region N1, the gate thereof is connected to a signal terminal 50c to which a reset gate Pulse .phi..sub.RS is applied, and the drain thereof is connected to a signal terminal 50b to which a reset drain voltage (voltage for charge drain) V.sub.RD is applied. The signal terminal 50c is connected to a supply source 5c of the reset gate pulse .phi..sub.RS, and the signal terminal 50b is connected to a supply source 5b of the reset drain voltage V.sub.RD.
Partial potential resistors R1 and R2 are connected in series between the supply source 5b of the reset drain voltage V.sub.RD and the ground, so that a DC bias voltage V.sub.BS is generated at the connection point of these resistors. A diode 54 is connected between the connection point of these resistors and the signal terminal 50c so that the forward direction is the direction from the connection point toward the signal terminal 50c.
The reset drain voltage V.sub.RD is a DC voltage of, for example, 15 V. The gate of the reset transistor 52 is normally applied with a gate application pulse .phi..sub.RS ' obtained by superimposing the DC bias voltage V.sub.BS on the reset gate clock .phi..sub.RS which is normally driven at 0 V to 5 V.
FIG. 12 shows the voltage relationship between the reset gate clock .phi..sub.RS and the gate application pulse .phi..sub.RS '. For example, under the conditions of V.sub.RD =15 V, R1=10 k.OMEGA., and R2=20 k.OMEGA., V.sub.BS is 10 V. Under these conditions, assuming that the high level and low level of the reset gate clock .phi..sub.RS are 5 V and 0 V, respectively, and the forward voltage of the diode 54 is -0.5 V, the amplitude of the gate application pulse .phi..sub.RS ' is from 9.5 V to 14.5 V.
The resistors R1 and R2 and the diode 54 are disposed externally although it is basically possible to mount these components on the chip, for the following reasons. In the case of on-chip formation, the resistors will be constructed so that the internal voltage V.sub.BS be generated by dividing the resistance of a low-concentration diffusion layer in consideration of current consumption. In this case, if the concentration of the diffusion layer varies during the fabrication process, the value of the internal voltage V.sub.BS also varies. As for the diode, if the diode is attempted to be formed on the CCD chip, the process becomes complicated because, while the diode is formed by a bipolar process, the CCD chip is basically formed by a MOS process. It is possible to form a transistor in place of the diode. In this case, however, the value of the internal voltage V.sub.BS still changes due to a variation in fabrication process.
Referring to FIGS. 8 and 9A to 9C, the operation of sweeping waste charges out from the charge accumulation region after charge-voltage conversion will be described. FIG. 8 shows a timing of a gate clock pulse .phi..sub.H1 for the horizontal CCD 3 and the gate application pulse .phi..sub.RS ' for the reset transistor 52 used during the operation of sweeping waste charges. FIGS. 9A to 9C illustrate potential states in a portion ranging from the downstream end of the horizontal CCD 3 to the reset transistor 52, at times t=t.sub.1, t=t.sub.2, and t=t.sub.3 indicated in FIG. 8, respectively.
In FIGS. 9A to 9C, the gate clock pulse .phi..sub.H1 is applied to two adjacent horizontal transfer gates 3a and 3b. In general, two adjacent horizontal transfer gates of the horizontal CCD are located on different semiconductor regions discriminated from each other by ion implantation so as to provide a potential gradient. In this case, boron is implanted in the semiconductor region underlying the horizontal transfer gate 3a. An output gate 7 is located near the horizontal transfer gate 3b. A constant DC voltage V.sub.OG is applied to the output gate 7. A charge accumulation region 51a of the floating diode is located between the output gate 7 and a gate 52a of the reset transistor 52.
A charge Ch accumulated in the horizontal CCD 3 at t=t.sub.1 is transferred to the diffusion layer (charge accumulation region) 51a called a floating diode, which is in a potential-floating state at t=t.sub.2 via the output gate 7 to which the DC voltage V.sub.OG of about 1 V to 2 V is applied. The potential at the floating diode varies depending on the amount of the transferred charge, and the variation of the potential is output to the output circuit 6. Thereafter, at t=t.sub.3, the waste charge is swept out to the reset drain. At this time, the potential at the floating diffusion layer 51a is also fixed to the reset drain voltage V.sub.RD.
The DC bias voltage V.sub.BS superimposed on the reset gate clock .phi..sub.RS, which constitutes the low level of the gate application pulse .phi..sub.RS ', is set so that the reset transistor 52 is turned on at the time of reset, i.e., when the reset gate clock .phi..sub.RS becomes a high level.
For example, assuming that the reset drain voltage V.sub.RD is 15 V, and the voltage level of the gate application pulse .phi..sub.RS ' for turning on the reset transistor 52 is Vt, the level required as the DC bias voltage V.sub.BS is (Vt-5.0)V when the amplitude of the reset gate clock .phi..sub.RS is from 0 V to 5.0 V. The DC bias voltage V.sub.BS is determined by the level of the reset drain voltage V.sub.RD and the properties of the reset transistor 52, such as the threshold of the transistor and the effect of the substrate on the transistor.
Actually, however, the supply voltage and the properties of the transistor 52 vary. Therefore, a value including such variations is normally selected as the DC bias voltage V.sub.BS to be superimposed, so as to ensure the reset operation. Specifically, the DC bias voltage to be superimposed is often set at a value higher than the above value (Vt-5.0)V by about 1 V.
FIGS. 10A to 10D illustrate the potential levels at a floating diode (FD) section, a reset gate (RG) section, and a reset drain (RD) section in the state where no charge is accumulated. The FD section corresponds to the charge accumulation region constituting the floating diode 51, the RG section corresponds to the region below the gate of the reset transistor 52, i.e., a channel region, and the RD section corresponds to the drain region of the reset transistor 52. In FIGS. 10A to 10D, P(.phi..sub.RS 'L) denotes a potential level at the RG section when the gate application pulse .phi..sub.RS ' is in the low level, P(.phi..sub.RS 'H) denotes a potential level at the RG section when the gate application pulse .phi..sub.RS ' is in the high level, and P(V.sub.RD) denotes a potential level at the RD section to which the reset drain voltage V.sub.RD is being applied.
FIG. 10A illustrates an ideal case, where the high level of the gate application pulse .phi..sub.RS ' should be such a voltage level that, when this voltage is applied to the gate 52a of the reset transistor 52, the potential level at the reset gate (RG) section is just matched with the potential level at the reset drain (RD) section to which the reset drain voltage V.sub.RD is applied.
When the reset drain voltage V.sub.RD supplied externally is varied on the increase side by .DELTA.V.sub.1 as shown in FIG. 10B, the potential levels at the floating diode (FD) section and the reset drain (RD) section increase, resulting in a failure to completely sweep the waste charge although the high level of the gate application pulse .phi..sub.RS ' applied to the gate 52a of the reset transistor 52 is kept unchanged.
When the threshold Vt of the reset transistor 52 increases due to a variation in fabrication process as shown in FIG. 10C, the channel potential decreases by .DELTA.V.sub.2 with respect to the ideal state although the voltage applied at the gate of the reset transistor 52 is kept unchanged. This causes a reset failure in which the waste charge cannot be completely swept, resulting in degradation of image quality.
In order to avoid such degradation of image quality, the variation in the reset drain voltage V.sub.RD and the variation in the threshold Vt of the transistor 52 due to a variation in fabrication process are taken into consideration in setting the DC bias voltage V.sub.BS superimposed on the reset gate pulse .phi..sub.RS. That is, the DC bias voltage V.sub.BS is set so that the potential is higher than the ideal case by about 1 V to compensate .DELTA.V.sub.1 +.DELTA.V.sub.2. FIG. 10D illustrates the potential levels at the FD section, the RG section, and the RD section observed when the above setting is performed. The DC bias voltage V.sub.BS set as described above is actually about 1 V higher than the ideal case although it depends on the process conditions.
However, if the reset drain voltage V.sub.RD is varied on the decrease side and the threshold Vt of the reset transistor 52 decreases due to a variation in fabrication process under the above conditions, the accumulable charge amount in the floating diode (FD) section decreases.
FIGS. 11A and 11B are views illustrating the accumulable charge amounts in the floating diode (FD) section: FIG. 11A illustrates the accumulable charge amount in the case where the DC bias voltage V.sub.BS is set to be higher by about 1 V than the ideal case. FIG. 11B illustrates the accumulable charge amount in the case where the DC bias voltage V.sub.BS is set to be higher by about 1 V than the ideal case and moreover the reset drain voltage V.sub.RD is varied on the decrease side, while the threshold Vt decreases, providing a total variation of about 1 V.
In general, as the DC bias voltage V.sub.BS is increased to prevent reset failure, the accumulable charge amount in the FD section is decreased since the accumulable charge amount is limited by the low level of the gate application pulse .phi..sub.RS '.
When the above accumulable charge amount in the FD section is considered, together with the variation in supply voltage and the variation in fabrication process, a loss of the voltage amplitude of about 2 V at maximum is generated. This is equivalent to applying a pulse having an amplitude of 3 V as the gate application pulse .phi..sub.RS ' in the ideal case.
Thus, the conventional solid-state imaging apparatus described above has the following problem. Although the amplitude of the gate application pulse to be applied to the reset transistor is 5 V, the actual effective amplitude of the gate application pulse is decreased to about 3 V due to a variation in the supply voltage connected to the drain of the reset transistor and a variation in the fabrication process for the reset transistor. This means, in reverse, that in the ideal state the reset operation requires only 3 V amplitude of the gate application pulse. However, since this ideal state cannot be realized stably, an amplitude of 5 V is required to be set as the gate application pulse.
Japanese Laid-Open Publication No. 4-360544 discloses a charge detection apparatus which can be normally operated only by continually supplying a binary pulse externally even if the channel potential of a reset transistor varies due to a variation in fabrication process (conventional example 2).
FIG. 13A illustrates a circuit construction of a charge detection apparatus 210 of the conventional example 2. FIGS. 13B and 13C illustrate the potential at the reset drain (RD) section and a channel potential during application of the gate application pulse .phi..sub.RS '. FIG. 13B shows the case where the channel potential is not varied due to a variation in fabrication process, and FIG. 13C shows the case where the channel potential is varied due to a variation in fabrication process.
A voltage generation circuit 201 includes: a voltage generation transistor 201a having a terminal connected to the input terminal 50b of a drain application voltage and a gate to which a DC voltage V.sub.ref is applied; an inverted amplifier 201b of which input is connected to another terminal of the transistor 201a; and a diode 201c connected between the output of the inverted amplifier 201b and the input terminal 50c for the reset gate clock. The voltage generation transistor 201a is fabricated in the same process as the reset transistor 52 and has the same construction as the reset transistor 52.
In the apparatus 210 with the above construction, the DC voltage V.sub.ref is set so that, when the gate application pulse .phi..sub.RS ' is in a high level, DC bias voltages V.sub.BS and V.sub.BS ' are generated on the input side and the output side of the inverted amplifier 201b, respectively. The DC bias voltages V.sub.BS and V.sub.BS ' should be high enough for the transistor 201a having a drain to which the voltage V.sub.RD is applied to be turned on. In this state, as shown in FIG. 13B, the channel potential P(.phi..sub.RS 'H) obtained when the gate application pulse .phi..sub.RS ' is in the high level is matched with the potential P(V.sub.RD) at the drain region of the reset transistor 52.
In this conventional case, when the channel potential of the reset transistor 52 is increased by .DELTA.P due to a process variation (see FIG. 13C), the channel potential at the voltage generation transistor 201a is also increased by .DELTA.P, and thus the DC bias voltage V.sub.BS on the input side of the inverted amplifier 201b is increased by .DELTA.V.sub.BS corresponding to the potential increase .DELTA.P.
In the above case, the output voltage V.sub.BS ' of the inverted amplifier 201b is decreased by a value corresponding to .DELTA.V.sub.BS, and thus the voltage level of the gate application pulse .phi..sub.RS ' is decreased, resulting in canceling the variation .DELTA.P of the channel potential.
The above conventional example 2 has the following problem. A variation is generated in the channel potential of the voltage generation transistor 201a due to a variation in fabrication process, as in the reset transistor 52, causing a variation in the output voltage V.sub.BS of the voltage generation transistor 201a. However, the direction of the variation in the output voltage V.sub.BS is reverse to the direction of the change in the voltage applied to the gate of the reset transistor 52 for canceling the variation in the channel potential at the reset transistor 52. An inverted amplifier is therefore required for inverting the output voltage V.sub.BS. Having the inverted amplifier, it becomes necessary to additionally consider a variation in the characteristics of the inverted amplifier.
Japanese Laid-Open Publication No. 6-133227 discloses a charge transfer apparatus having a voltage generation circuit incorporated in a CCD chip (conventional example 3).
FIG. 14A illustrates a circuit construction of a charge transfer apparatus 220 of the conventional example 3. FIGS. 14B and 14C illustrate the potential at the reset drain (RD) section and a channel potential during application of the gate application pulse .phi..sub.RS '. FIG. 14B shows the case where the channel potential is not varied due to a variation in fabrication process, and FIG. 14C shows the case where the channel potential is varied due to a variation in fabrication process.
The difference in construction of the conventional example 3 from the conventional example 1 shown in FIGS. 7A and 7B is as follows. A voltage generation transistor 202a is connected between the reset transistor 52 and the input terminal 50b for the drain application voltage, so as to incorporate a voltage generation circuit 202 for generating a drain voltage for the reset transistor 52 in a CCD chip 220a. The voltage generation transistor 202a is fabricated in the same process as the reset transistor 52 and have the same construction as the reset transistor 52.
With the above construction, an output voltage V.sub.RD ' of the voltage generation circuit 202 is lower than the reset drain voltage V.sub.RD supplied externally by a threshold Vt(V.sub.RD) of the transistor 202a.
The level of the DC bias voltage V.sub.BS to be superimposed on the reset gate clock .phi..sub.RS is set in the above state. Although the publication which discloses the conventional example 3 mentions no generation circuit for the DC bias voltage V.sub.BS, it is clear from the technical aspect of the publication that a generation circuit for DC bias voltage V.sub.BS is necessary.
When the channel potential of the reset transistor 52 is increased by .DELTA.P due to a process variation, the potential P(V.sub.RD ') at the drain region of the reset transistor 52 is also increased by .DELTA.P.
In the conventional example 3, therefore, even if the channel potential of the reset transistor 52 is varied due to a process variation, the difference between the potential at the drain region of the reset transistor 52 and the channel potential of the reset transistor 52 during application of the high-level and low-level gate application pulse .phi..sub.RS ' can be fixed.
One problem of the above conventional example 3 is that the V.sub.BS generation circuit is additionally required. Another problem is as follows. The conventional example 3 describes that the potential at the source region of the voltage generation transistor 202a is the same as the channel potential below the gate of the transistor 202a. However, since the diffusion layer constituting the source region is in the potential-floating state, it finally falls in the same potential as that at the diffusion layer constituting the drain region at which the potential is fixed by an external source, during the thermionic emission. To avoid this, some measures must be taken to keep the potential at the source region identical to the channel potential.
As one of the measures, Japanese Laid-Open Publication No. 6-153086 discloses a method in which a charge is periodically supplied from an external source, i.e., through the drain region to the source region, during a time period when the output from a CCD is unnecessary (e.g., during a horizontal return period), so that the potential at the source region is made identical to the channel potential (conventional example 4).
Japanese Laid-Open Publication No. 9-130681 discloses a solid-state imaging apparatus which integrally overcomes the problems arising in the above conventional examples 1 to 4 (conventional example 5). As shown in FIG. 15, the conventional solid-state imaging apparatus of the conventional example 5 includes a pulse generation circuit 203 incorporated in a CCD chip 230a, in place of the diode 54 for generating the DC bias voltage V.sub.BS and the resistors R.sub.1 and R.sub.2 in the solid-state imaging apparatus 200 of the conventional example 1. The pulse generation circuit 203 receives the reset gate clock .phi..sub.RS and generates the gate application pulse .phi..sub.RS '. The other construction of the solid-state imaging apparatus 230 is the same as that of the solid-state imaging apparatus 200 of the conventional example 1.
The pulse generation circuit 203 includes: a voltage generation transistor 203a of which a drain D1 is connected to a drain D2 of the reset transistor 52 and a source S1 and a gate G1 are connected to a gate G2 of the reset transistor 52; and a resistor 203b connected between the drain D2 and the gate G2 of the reset transistor 52.
The above construction realizes the ideal state shown in FIG. 10A in the conventional example 1, in which the pulse amplitude of 5 V of the reset clock pulse conventionally required can be reduced to about 3 V, thereby enabling low voltage and low power consumption. Also, in this construction, a generation circuit for the DC bias voltage V.sub.BS to be superimposed on the reset pulse, which is conventionally required to be disposed outside the CCD chip, is not necessary, thereby enabling reduction in the number of peripheral components and thus reduction in the size, weight, and cost of the apparatus.
However, the conventional example 5 has the following problem. The transistor in the pulse generation circuit 203 incorporated in the CCD chip has such a structure that the gate and the source are short-circuited. Accordingly, in order to prevent short-circuiting between the drain and the source, the transistor needs to be an n-channel type in which the channel potential below the gate is lower than the gate voltage. Therefore, the conventional example 5 is not applicable to apparatuses in which the channel potential of the transistor is higher than the gate voltage thereof.